- Audio Spectrum Analyzer - OscilloMeter
Audio Spectrum Analyzer for Real-time, FFT, OscilloScope, Frequency counter, voltmeter, noise and distortion meter, phase shift meter. Multi-Tone Sound Frequency Sweep Generator. White, pink noise.
Zelscope is a Windows software that converts your PC into a dual-trace storage oscilloscope and spectrum analyzer. It uses your computer's sound card as analog-to-digital converter, presenting a real-time waveform or spectrum of the signal - which can be music, speech, or output from an electronic circuit.
Oscilloscope, Realtime spectrum analyzer, Impedance meter, RLC bridge and signal generator for Windows. Is a Windows application that converts your PC into a powerful dual-trace signal analyzer (oscilloscope, FFT etc...) . Uses your PC sound card as an Analog-to-Digital a Converter to digitize any input waveformand as Digital-to-analog Converter for the signal generator.True 24 bit adc/dac 48K/96k/192k sampes/sec.
- Android Oscilloscope- Run an oscilloscope under your Android phone
- Audio Spectrum Analyzer - OscilloMeterpop- Audio Spectrum Analyzer for Real-time, FFT, OscilloScope, Frequency counter, voltmeter, noise and distortion meter, phase shift meter. Multi-Tone Sound Frequency Sweep Generator. White, pink noise.[ Hits: 88827 Votes: 325 Rating: 6.2 ]
- Baudline signal analyzer- A Linux based FFT spectrum analyzer designed for time-frequency browsing and scientific data visualization. Oscilloscope waveform, statistical histogram, accumulated spectral trace,Weak Signal reception, continuos data logging, FFT Analyzer and specialized measurement windows.
- BIP Electronics Lab Oscilloscope- Freeware windows oscilloscope uses the sound card's input to measure signals. This means that the quality of the scope depends on the quality of your sound card.The scope automatically uses the highest sample frequency available at the input that you select[ Hits: 9916 Votes: 16 Rating: 5.5 ]
- Cleverscope - The PC USB mixed signal oscilloscope- Cleverscope PC based oscilloscopes, spectrum analyzers and signal generators
- Cobracom- Oscilloscope, Realtime spectrum analyzer, Impedance meter, RLC bridge and signal generator for Windows. Is a Windows application that converts your PC into a powerful dual-trace signal analyzer (oscilloscope, FFT etc...) . Uses your PC sound card as an Analog-to-Digital a Converter to digitize any input waveformand as Digital-to-analog Converter for the signal generator.True 24 bit adc/dac 48K/96k/192k sampes/sec.[ Hits: 21042 Votes: 13 Rating: 6.23 ]
- Digital Oscilloscope and analyzer software- PC based mixed signal digital oscilloscope and analyzer software for BitScope. Runs on Windows, Linux or Mac OSX systems.
- Oscilloscope Software by Tektronix- Tektronix oscilloscope software helps automate and speed up the testing and evaluation of challenging system designs. Choose from over 30 software packages[ Hits: 2458 Votes: 3 Rating: 6.67 ]
- PicoScope- Pico Technology have developed a wide range of professional PC-based instruments that offer all the functionality of conventional test equipment (DSO - digital storage oscilloscope, spectrum analyzer, meter), and also many features not normally available in this price range. Available functios are Oscilloscope, Spectrum Analyser, XY Scope, Meter and Measurements
- ScopePar- ScopePar turns your old PC into a multi-channel oscilloscope, the user-interface to which is SeriCon on Windows PC.[ Hits: 5474 Votes: 1 Rating: 1 ]
- Soundcard Oscilloscope- PC based Soundcard Oscilloscope software that receives its data from the Soundcard with 44.1kHz and 16 Bit resolution.
- USBee- PC and USB Oscilloscope, Logic Analyzer, Signal Generator and Protocol Decoder and Analyzer[ Hits: 5912 Votes: 4 Rating: 8.25 ]
- Virtins Technology- Offer PC based virtual instrument for electronics enthusiasts, students and professionals, including full-fledged sound card real time Oscilloscope, Spectrum Analyzer and Signal Generator.
- Xoscillo- A multiplatform software oscilloscope and logical analyzer software that acquires data using an arduino or a parallax USB Oscilloscope[ Hits: 2210 Votes: 0 Rating: 0 ]
- xoscope for Linux- xoscope (or oscope) is a digital oscilloscope for Linux
- Zelscopepop- Zelscope is a Windows software that converts your PC into a dual-trace storage oscilloscope and spectrum analyzer. It uses your computer's sound card as analog-to-digital converter, presenting a real-time waveform or spectrum of the signal - which can be music, speech, or output from an electronic circuit.[ Hits: 70574 Votes: 25 Rating: 5.09 ]
- ZScope- ZScope oscilloscope software is free with the purchase of any ZTEC oscilloscope available in PCI, PXI, VXI, & LXI. Remote control ZTEC oscilloscopes.
Low distortion Arbitrary Waveform Generator. The Handyscope HS5 is the first High Resolution USB oscilloscope with built-in 30 MHz low distortion function generator. The built-in Arbitrary Waveform Generator uses CDS signal synthesis technology, developed by TiePie engineering, resulting in the best signal fidelity in its class, generating the true form of your signals.
- A V Signal 64 bit download - page 5 - X 64-bit Download - x64-bit download - freeware, shareware and software downloads.
- The package you are about to download is authentic and was not repacked or modified in any way by us. Each download we provide is subject to periodical scanning, but we strongly recommend you check the package for viruses on your side before running the installation. The version of the program you are about to download is 184.108.40.2064.
Search The DXZone.com
Software : Oscilloscope
About The DXZone.com
Download Cleverscope Driver App
Sign up for daily Newsletter
Download Cleverscope Driverpack
Free for your Site
Download Cleverscope Driver License
This is only a preview of the October 2018 issue of Silicon Chip.
You can view 40 of the 112 pages in the full issue and the advertisments.
For full access, purchase the issue for $10.00 or subscribe for access to the latest issues.
Items relevant to 'GPS-synched Frequency Reference Pt.1':
Items relevant to 'Arduino-based programmer for DCC Decoders':
Items relevant to 'Low-voltage, high-current DC Motor Speed Controller':
Items relevant to 'Opto-Isolated Mains Relay':
Items relevant to 'Intro to programming: Cypress' System on a Chip (SoC)':
A 5-year design odyssey:The CS448 1kV isolated4-channel oscilloscopeIf you open up a piece of modern test equipment, such as a spectrumanalyser or oscilloscope, you will beamazed at the sheer number ofcomponents, the intricacy ofthe layout and the hugeamount of work whichmust have gone into itsdesign. Here’s a rareglimpse into the challengeswhich Bart Schroeder, ofCleverscope, had toovercome in designing their latest product, a USB ’scope with particularlystrict performance requirements. He tells the story in his own words . . .Wpeople will find it interesting and enlightening.ay back in September 2011, I was at the ElectroneX show in Melbourne demonstrating ourDetermining the requirementsCS328A two-channel, 100MHz USB scope. RatherThe key specifications we came up with for the scope,than resting on my laurels, I started to plan our next product.based on the requirement for working with a VSD, were:This would be a four-channel scope with each channel• A ±800V range, adequate for probing circuits like moproviding 1kV isolation from the others, and from the hosttor speed controllers which are powered from rectifiedPC. Having isolated channels makes a scope much morethree-phase mains.versatile since it frees you up to probe voltages across any• 1 part in ±8000 resolution (1 part in 16000). This requirescomponent in a circuit. This is especially useful when worka 14-bit analog-to-digital converter (ADC; 214 = 16384)ing on motor speed controllers, especially variable-speedwith very low noise. The result will be a voltage resodrives (VSD) – see the panel below for details.lution of 0.1V on the ±800V range. Less than two LSBAs well as adding two channels and providing the iso(least significant bits) RMS noise would be good, givinglation, the new scope would also have significantly bettera usable resolution of 0.2V – just enough for accuratelyresolution and bandwidth than our then-current models.measuring the current through floating low-value shunts.It would be by far our best offering.• Less than 1% error when measuring the current through aI had no idea at the time that it would take so long tolow-value sense resistor withachieve this! I was finally ablea 1x probe while slewing overto reveal our new high-perfora 680V range (ie, full-wavemance CS448 PC-based scopeThe Cleverscope CS448 is most definitely NOT rectified mains).at PCIM in Nuremberg, Ger• An input capacitancemany in July 2017.a ’scope you would find on many workbenches.×10pF to limit common modeIt has been a learning expeIndeed, its price alone (more than $13,000capacitively-coupled currentrience for me and I have a lotplus options!) would strongly suggest that.to a tolerable level.more grey hair than I did fiveHowever, for engineers, design labs, QC/QAyears ago.ADC selectiondepartments and other “high end” users itIn this article, I will describeThe first question wasthe journey from idea to finwould be very high on their “wish list”.whereto put the ADC; onished product and some ofThe Cleverscope CS448 is right up there withtheisolatedside, or the nonthe pitfalls that I encounteredother “professional” scopes; – there aren’tisolated side. The noise flooralong the way. I want to sharesets the dynamic range and isthe story since I think many many that can beat it at anything like the price!WHO’S IT INTENDED FOR?68Silicon ChipAustralia’s electronics magazinesiliconchip.com.auInside the CS448 (shown here about 2/3 life size). Of particular note is the extensive shielding and the fibre optic links.The five symmetrical transformers transmit power to the isolated inputs and signal generator.related to the number of components between the inputand the ADC. A reduced component count means lowernoise and since low noise was a requirement, that meantthat the ADC needed to be on the isolated (ie, input) side.We already determined that our ADC needed a resolution of at least 14 bits. And it would help for it to be a lowpower device because we have to get its power across theisolation gap. We would also need a method for sendingthe digitised signal to the non-isolated side.The only realistic transfer method is via an optically isolated serial bus and the only standard method that allowssynchronization (which is important in a multi-channelscope) is JESD204B, a standard for ADC and DAC datatransfer.The scope also incorporates a signal generator and digital input. Multiple units can be linked together.siliconchip.com.auAustralia’s electronics magazineOctober 2018 69Variable Speed Drives and H-bridgesThe idea for the CS448 Isolated Channel Oscilloscope cameto me when I was designing Variable Speed Drives (VSDs)for electronic motor speed control. A VSD uses three halfbridges to generate a three-phase signal to control the rotation of a three-phase motor.SILICON CHIP has published a three-phase VSD design inthe past, the Induction Motor Speed Controller from theApril and May 2012 issues (later updated in the December2012 and August 2013 issues). It uses an integrated threephase bridge containing six IGBTs (insulated gate bipolartransistors, a BJT/Mosfet hybrid device), drivers and controlling circuitry.You can also use two half bridges to control a steppermotor or permanent magnet DC motor. This is called a fullbridge or H-bridge. Each half-bridge uses two transistors toswitch one side of the load between a negative and positivesupply voltage. The half-bridge is sometimes known as a“totem pole” arrangement, as the two transistors are stackedbetween the supply rails.Fig.1 shows a full bridge circuit built using Mosfets andhalf-bridge gate driver ICs, which switches the voltage acrossZload. Normally, one end of Zload is connected to +VBUS andthe other end, to -VBUS.When Q1 and Q4 are switched on (and Q2 and Q3 off),current flows from +VBUS to -VBUS through the path indicated by the solid grey line, with the red probe giving a readingnear +VBUS and the blue probe near -VBUS.In contrast, when Q2 and Q3 are switched on (and Q1and Q4 off), current flows through the path indicated by thedashed grey line, with the red probe reading near -VBUS andthe blue probe near +VBUS. In other words, current flowsthrough Zload in the opposite direction in this case.If you alternate between these two conditions rapidly, theinductance of Zload (which is normally a motor coil) causesthe current to increase or decrease more slowly and so bycontrolling the percentage of time spent in each state (usingpulse width modulation [PWM]), you can vary the voltageacross Zload smoothly.The voltage is normally made to vary in a sinusoidalmanner, with a frequency determined by the desired motor rotation speed.Design challengesThat all sounds pretty nice and neat but in the real world,designing a good bridge circuit and controlling it properlyis not that easy. For example, when switching between thetwo states, you need to make sure that you never have bothQ1 and Q2 on at the same time, or else current will “shootthrough” them from +VBUS to -VBUS and they will heat upand possibly fail. The same applies for Q3 and Q4.But at the same time, you want to transition betweenthe two states as rapidly as possible for maximum efficiency. So you really need to tune the Mosfet gate drive to suitthe particular devices. You have to keep in mind the gatecharge and discharge times as well as the Mosfet switch-onand switch-off times (which are all different and can varybetween samples of the same device).And with the high voltages, currents and fast slew rates,you have all sorts of other factors such as parasitic capacitance within the Mosfets and between tracks and compo70Silicon ChipFig.1: a typical H-bridge driver. Because the load is“floating”, using a traditional ’scope will not give usefulreadings . . . and might let the smoke escape!nents, which cause induced voltages to appear in places whereyou may not necessarily expect them.The bottom line is that when you are developing this typeof motor drive, you really need to be able to observe its behaviour and that means monitoring the gate drive waveforms, thevoltage across the motor winding(s) and the current througheach device. And once you have done this with a dummyload, you also need to test with a real motor – this is knownas functional testing.You have to make allowances for temperature, componentvariation and drift. All this is virtually impossible if you can’tuse an oscilloscope to measure the signals at various pointsin the circuit and make sure they are correct and match yourdesign calculations.The ground reference bugbearBut, and it’s a big but, in circuits like this, many of the signals you are interested in are not ground referencedUnfortunately, most scopes have ground-reference inputs.Look at the purple and green probes in Fig.1, which aremeasuring the gate drive for high-side Mosfets Q1 and Q3.These voltages are relative to the sources of those FETs, at thered and blue probes, which are switching rapidly between-VBUS and +VBUS.You could “float the scope” by powering it from an isolating transformer but that only gives you one floating channel,and besides, it’s dangerous, and there might be quite a highcapacitance or inductance to ground through the power supply, which would cause very high currents to flow through theprobes, possibly causing damage.FETs (including GaN and SiC varieties) can switch in 10100ns. If the switching time is 10ns, with 100pF capacitanceand a 680V bus, you’ll get 6.8A (CV÷dt = 100pF x 680V ÷ 10ns)!So you really need a low capacitance to Earth.The traditional way to overcome these limitations is touse a differential probe but even a good one will have a poorCommon Mode Rejection Ratio (CMRR) at high frequencies.As an example, the Tektronix P5200A has a CMRR of 30dB at3.2MHz. 3.2MHz equates to a rise time of tr 100ns (1÷Δf). Lotsof modern transistors switch faster than that.Australia’s electronics magazinesiliconchip.com.auIf you had a 680V bus (as is typical for three-phase powersupplies), the probe will generate a spurious signal equal to680V <at> -30dB = 0.032 x 680V or 21.8VThat’s a larger magnitude than the signal you’re actuallytrying to probe so it will obliterate it! Why measure the gatedrive you say? After blowing up quite a few IGBT modules,I can tell you that the gate drive has to be right.Adequate signal resolutionIt’s also important to ensure that there was not too muchpower loss in the transistors. Running the motor and having the switching devices blow up is not the best way totest this! A better way is to measure the voltage across thetransistor while measuring the current through it and multiply to get power.Referring to Fig.2, this means that you need to measure VDSacross the transistors as well as the voltage across the drainresistors, which is a proxy for the current through the transistor. These resistors are typically low value (1-10mΩ) types.VDS will transition between the saturation voltage, say 0.23V and the off state voltage, say 680V. So you really need aresolution of 0.1V, or one part in 6800, to measure this accurately. Your average scope has an 8-bit ADC, giving onepart in 256 resolution.Assuming that the input range is close to 680V, the resolution will be 2.6V and noise will mean that the actual practical resolution is at least 5V. That’s not very useful.So to really see what is going on in this H-bridge, we needan isolated scope with good CMRR at high frequencies andhigh enough resolution to do 1 part in 6800. If you now lookat the target specifications for the CS448 scope at the startof this article, you will see that they are all based on the requirements of working with this type of circuit.Having said that, this is far from the only situation inwhich you will need these capabilities. Many circuitshave sections that are floating or which have different local grounds, and high-side shunts are quite common. Ascope with isolated channels is very helpful in these cases. And a good CMRR, high resolution and low noise areall desirable attributes no matter what you are probing.After a search, we settled on the Intersil ISLA214S50ADC, a 500Msps 14-bit ADC which could transfer all thesamples over two serial lanes, at 4.375 Gbps per lane (using data compression).The ADC needs a buffer/amplifier in front of it and thebest part we could find for this job was the Analog DevicesADA4817, a 1GHz bandwidth FET-input op amp. This hasjust 4nV÷√Hz voltage noise, low distortion and a good slewrate. We matched this with the ADA4937 differential ADCdriver, with only 5.8nV÷√Hz output noise, 1.9GHz bandwidth and -102dB (<0.001%) distortion.We talked to Analog Devices and discovered that theADA4817 included an input analog multiplexer, so theplan was to have two ranges and use the multiplexer toswitch between them to keep everything as simple as possible. We’d make the ranges ±800mV and ±8V.With these two ranges, we could use a 10:1 probe to get±8V or ±80V with full bandwidth and the ±800mV rangewould work well with current sense resistors, giving a100µV resolution. A 100:1 probe would give us a ±800Vrange and some combination of these probes would coverjust about every situation.IsolationWe did a market search looking for the best way to transmit the two serial data streams to the FPGA (field-programmable gate away) that would be used to control allthe scope functions.Eventually, we found an English company, AdvancedFibreoptic Engineering, who could make us pairs of optically isolated transmitters and receivers with a holder andfibre links between them.We paired these with the Texas Instruments ONET4291VA transmitter driver and limiting amplifier receiver.It sounds simple but it wasn’t!Clock generationWe wanted all four channels to use the same clock sourceso that they would be perfectly synchronised but that wouldhave meant another fibre channel and anyway, the jitter ona fibre channel is way too high for precise timing. In effect,our 14-bit ADC would become an 8-bit ADC.So we settled on using a programmable clock oscillator(the Silabs Si598) as the low-jitter clock source. The ideawas that we could measure the channel frequency fromthe serial data coming back and adjust the clocks to makethem all the same.Power supply and other detailsFig.2: high side gate drive waveforms – the parasiticeffects are the big deal!siliconchip.com.auAs we said above, a low capacitance between the channel common (- input) and the real system ground is absolutely critical. This capacitance is determined by the powertransformer inter-winding capacitance and the capacitancebetween the channel components/tracks and the chassis,plus the capacitance of the scope probe to the surrounding environment.We can control the power transformer and the channel placement. We decided to use a Maxim MAX13256H-bridge driver to provide the isolated supplies for eachchannel with the companion Halo TGMR-501V6LF lowcapacitance (10pF) capacitor as specified in their literature. The transformer chosen was UL/EN60950 approved,which we needed.Australia’s electronics magazineOctober 2018 71Fig 3: clock jitter reduces the usable resolution of the ADC.The jitter from our clock generator is very low and does notadversely affect ADC performance.We decided to use a cheap-as-chips STM8 8-bit microcontroller for channel control, communicating via an optoisolated serial link with the system FPGA.Most scopes offer 1MΩ and 50Ω input impedances, sowe put in a relay in each channel to switch in the 50Ω. Youneed a relay to switch the 50Ω resistor in and out, to ensure low parasitic impedance and capacitance.We knew we’d need shielding to stop noise from allthose high-frequency FPGA signals from getting into thesensitive analog front end. So we design a U-shaped shieldwith fingers which could be pushed down through slots inthe board, to make a shield right around the board. Thiswould mate with a ground plane on the main board thatthe digitiser would be plugged into.Building a prototypeWe put a lot of time and effort into designing and building a prototype, only to find that it a lot of problems! But Iguess you only find problems by building something andthen you have to learn from that and revise your design.The problems we found included:• The ADA4817 has bugs in it – the multiplexer did notwork as specified and when the device was disabled,it dragged the inputs to -5V instead of the inputs goinghigh-impedance. I was able to contact the designer of thechip at Analog Devices and they confirmed our findings.That means that our two-range design was unusable.• The MAX13256 H-bridge driver and transformer generated large common mode transients on the isolatedground which added to any signal being measured. Ourpower supply design was simply not suitable• The relay and 50Ω load resistor could not be turned offfast enough when the 1kV maximum input voltage wasapplied, with the resistor and relay disappearing in a puffof smoke. We had to abandon a 50Ω input impedanceoption. (Users could still connect a 50Ω terminator tothe input if you really needed it, with the responsibilityfor possibly blowing it up being with them!)• The Si598 clock generator output drifted at the rate ofabout 15Hz/second, which meant that long durationcaptures would not have inter-channel synchronisationafter 60 milliseconds or so. It also meant our intent todo Frequency Response Analysis (FRA) would fail. Weneeded a better clocking system.72Silicon ChipFig 4: common mode rejection ratio is below -115dBc allthe way to 65MHz in the unit being tested here. This is waybetter than just about any differential probe you’re likelyto come across – even those costing many thousands ofdollars. And a differential probe only gives you a singleisolated channel – this scope has four!• The ISLA214S50 ADC lost gain/offset alignment betweenthe two internal ADC’s used to achieve 500MSPS and became horribly non-linear if the signal exceeded the inputrange by even 1mV. This meant that we could not use theADA4937 differential amplifier because input overloading is very common when a user is looking at a portionof a signal. We needed to add components to limit theinput signal, to keep it within the ADC’s specified range• The shielding was good for stopping noise but uselessfor achieving a good CMRR. Because the shield was referred to the system earth, any capacitance between components on the board and the shield injected current intothe front end circuit, polluting the measured signal. Weneeded a better shield design.• We had different RC time constants between the AC andDC paths in our two ranges. These generated slowly rising or falling pulse responses when using 10:1 probes.Of these problems, the power supply was the most serious and hardest to fix.Making an isolated supply that injects only microvoltsinto the system being measured became one of the mostdifficult challenges of the whole design.Coming up with a better designIn the end, we went through three major versions of thescope, with two tweaks to the last version, before we were100% happy with the performance.The power supply took a year to completely sort out.The main lesson learned during this process was that itwas absolutely vital to keep everything symmetrical! Youneed a very symmetrical power switch, controlled equalslew rates on the power switch edges and a symmetricalpower transformer (see photo of main PCB).The transformer needs to be balanced and centre-tappedwith minimal inter-winding capacitance. Our final designhas two very widely separated winding with a very low capacitance between them. The windings are wound bifilarso that each half of the winding is symmetrical to the other.The clock system also needed a considerable amount ofwork. The only way to have all the clocks synchronisedwas to have a common clock. This meant that we had touse the FPGA as a clock master and distribute that clockto all the channels. This approach means we can also synchronise more than one scope together, effectively turningAustralia’s electronics magazinesiliconchip.com.auADA4817At left is the original inputPCB which looked good onpaper but had a numberof shortcomingswhich we had toaddress. The finalversion of the boardADA4817is shown at right– there’s a lot moreperformance50 OHMpacked intoRELAYthis one!shows the Murata FOTs and the interconnecting optic fibre. You can also see the 1kV isolation gap and the isolation power transformer.ShieldingSTM8ADA4937Si5344STM8ISLA214S50Si598ONET4291VAONET4291VAPOWERTRANSFORMERAC/DCSWITCHPOWERTRANSFORMERThe shielding is absolutely crucial to getting a good common-mode rejection ratio (CMRR); in other words, to preADA4817 vent changes in the channel ground relative to Earth fromshowing up in the differential signal.LMH6553The key is that the common-mode current (due to thechannel capacitance, as described earlier) must flow alongthe outside of the shield to the common point, which isISLA214S50 the centre tap of the isolation transformer. From there, itflows through the transformer inter-winding capacitanceto the case.The shield goes right around the PCB and is soldered tothe BNC socket shields. It incorporates a heatsink for theADC and clock generator chips. The plastic cover is to provide the required 1kV isolation.FIBREFIBREONET4291PA(2x under)FOTtwo 4-channel scopes into one 8-channel scope.So we needed another optic fibre isolated channel between the FPGA and each input channel to carry the clocksignal, which is a 100kHz square wave generated by theFPGA. This is then fed to an SiLabs Si5344 PLL/jitter attenuator and multiplied by a factor of 5000, resulting in a500MHz clock for the ADC.The Si5344 is a truly magical device; its output has a jitter of below 0.1ps. That is good enoughfor an 85dB signal-to-noise ratio when sampling at100MHz, which is more than the ADCs are capable of,so it does not compromise its performance (see Fig.4).The Si5334 output is precisely in-phase with the 100kHzmaster clock, meaning all four channels (and any downstream units) are properly synchronised.Range switching and isolationWhile the multiplexer in the ADA4817 does not work,the part is otherwise very good and so we decided to keepit. That meant that we needed a new scheme to switch input ranges.We ended up doing this using RF photomos switches,which are a similar to optocouplers (the two white packages). We used a clamping LMH6553 differential ADCdriver to avoid saturating the ADC, solving the problemsmentioned above, and we got rid of the 50Ω option sincethere was no way to make it failsafe.We determined that our two-way fibre isolator was nowlimiting the performance of the scope. Murata in Japancame to the rescue with Fibre Optic Transceivers (FOTs)and interconnect fibre. These dual-channel, bidirectional10Gbps units have only 60ps edge uncertainty variationbetween units.This meant that we could do a good job of synchronizingour 2ns clock periods; our final system achieves ±160psphase variation between channels. The adjacent photosiliconchip.com.auThe end resultThe final design is shown in the photo at left. It’s alwaysgood to end with something which works well, especiallyafter putting in so much effort. Fig.4 shows the measuredCMRR for Channel D of the CS448 scope with serial number EQ10019. It’s above 110dB right up to 65MHz! Thereare slight variations from unit to unit but they all exceed100dB up to 65MHz.110dB down from 680V is 2mV. With a 10:1 probe, thatmeans you have a useful resolution of about 20mV, whichis more than good enough for examining floating gate voltage signals, as we shall demonstrate below.Alternatively, if you are using a 1:1 probe to measure thevoltage across a current sense resistor, given the typical 1%accuracy, that means you can measure around 200mV fullscale, which equates to 100A through a 2mΩ shunt. Thatsounds pretty useful to me.Now for some real measurements demonstrating just howhandy the CS448 scope is. Fig.2 shows a direct measurement of two Mosfet high-side gate drives, where the common (bridge output) is slewing 500V in 8ns, as shown atthe bottom of the plot on page 71.We can clearly see the Miller plateau (where the gatevoltage stops rising as the gate charges up) on Gate 1 (orange trace) and the droop caused by the parasitic capacitive voltage divider formed by the Mosfet’s inherent gatedrain and gate-source capacitances, through which currentflows as the Mosfet switches on, affecting the drain-sourcevoltage as the switch goes high.Similarly, on Gate 2 (green trace), we see a pulse causedby the capacitive divider as the corresponding output (bluetrace) goes low. We have never seen plots of actual gatemeasurements as detailed and accurate as these for such ahigh-voltage bridge slewing so quickly. Many such measurements that you see are swamped by noise and commonmode signals.ConclusionIt was a lot of work but I am very pleased with the performance of the new scope.You can get more information about the CleverscopeCS448 from the company’s website at:https://cleverscope.com/products/CS448SCAustralia’s electronics magazineOctober 2018 73This content requires the Adobe Flash Player. Get Flash